1. Field of the Invention
The present invention generally relates to an electronic package. More particularly, the present invention relates to an electronic package with a passive component.
2. Description of the Related Art
Passing with the development of electronic technology, electronic products with multiple function are continuously released and have a trend with lightness, thinness, shortness and smallness. A circuit carrier, such as printed circuit board (PCB) or chip carrier, is commonly used in an electronic package. The circuit carrier is mainly composed of multiple patterning circuit layers and multiple dielectric layers that are provided with a stack by turns. The dielectric layer is deposited between the neighboring patterning circuit layers. Multiple plated through holes or vias formed through the dielectric layers connect the patterning circuit layers. The circuit carrier is widely used in various electronic packages, such as ball grid array (BGA) package or pin grid array (PGA) package. Passive components, such as capacitor, can be mounted on the circuit carrier to improve the quality of signal transition. The cross talk created with signal switches can be alleviated, for example.
FIG. 1 is a cross-sectional view depicting a conventional electronic package with a passive component. Referring to FIG. 1, the conventional electronic package 100 includes a circuit carrier 110, a chip 120 and a passive component 130. The circuit carrier 110 has a first surface 110a on which the chip 120 is mounted using an adhesive layer 150. Multiple wires 160 are formed to connect the chip 120 to the circuit carrier 110 using a wire bonding process. One or more passive components, such as capacitor, inductor or resistor, are electrically connected on the first surface 110a of the circuit carrier 110 by means of solder 140. A molding compound 170 encapsulates the passive component 130 and the chip 120. The circuit carrier 110 has a second surface 110b on which multiple solder balls 180 are mounted on the second surface 110b of the circuit carrier 110.
Referring to the magnified view at right side of FIG. 1, a patterning circuit layer 112 and a solder mask layer 114 are formed on a surface layer of the circuit carrier 110. The patterning circuit layer 112 has a passive-component-pad set 112a including a first pad 112b and a second pad 112c. The solder mask layer 114 is formed on the patterning circuit layer 112 and has opening exposing the first pad 112b and the second pad 112c of the passive-component-pad set 112a. 
The passive component 130 has a first electrode 130b and a second electrode 130c that are electrically and physically connected to the first pad 112b and the second pad 112c respectively by solder 140. In the process of bonding the passive component 130 onto the circuit carrier 110 using a reflow method, the solder 140 has flux for enhancing the bonding between the first electrode 130b and the first pad 112b and between second electrode 130c and the second pad 112c. After the passive component 130 is bonded onto the circuit carrier 110, the flux remaining on the circuit carrier 110 should be removed in a clean process.
Referring to the magnified view at right side of FIG. 1, the flux flowing into the gap between the passive component 130 and the solder mask layer 114 may not be easily removed because the gap is very small. Moreover, in the encapsulating process, the molding compound 170 doesn't easily flow into the gap between the passive component 130 and the solder mask layer 114. When the electronic package 100 experiences a high-temperature process once more, such as reflow process, the solder 140 formed on the first pad 112b and the second pad 112c may be melted again and then may flow into the gap between the passive component 130 and the solder mask layer 114 so that a short circuit may be created between the first pad 112b and the second pad 112c through the solder 140, leading the passive component 130 to be inactive. Namely, this is called the solder bridge issue. More particularly, the circuit carrier 110 and the passive component 130 develop following the trend of fine pitch with a shorter and shorter distance between the first pad 112b and the second pad 112c of the circuit carrier 110. The flux flowing into the gap between the passive component 130 and the solder mask layer 114 may be more difficultly removed, leading the solder bridge issue to occur when the passive component 130 is bonded onto the circuit carrier 110 using a soldering process.
The passive component 130 may be mounted under the wires 160 for reducing the area of the electronic package. When the wires 160 sag, they may contact with one of the electrode of the passive component 130, creating a short circuit. Therefore, the wires 160 should be formed with a large height. However, this may cause the wires 160 to be shifted during encapsulating the molding compound 170, so the neighboring wires 160 may be led to become a short circuit.
In the prior art, the solder 140 is formed on the first pad 112b and the second pad 112c of the circuit carrier 110 using a printing process. In the printing process, solder paste is first deposited on a stencil placed on the circuit carrier 110. Then, the solder paste is filled into multiple openings in the stencil with scraping the solder paste on the stencil to form the solder paste on the first pad 112b and the second pad 112c of the circuit carrier 110. The solder 140 is formed out of the solder paste using a reflow process. However, after exposed to the air, the solder paste is gradually worse and worse. The solder paste should be thrown away if it still remains in a term after the bottle filled with the solder paste is uncovered. Moreover, only few passive components 130 should be mounted on the circuit carrier 110 using a soldering process, so much solder paste may be left and should be abandoned. As a result, the cost of mounting the passive component 130 is raised.
In order to solve the above problem, chemical-plating processes have been proposed for plating the metal layers. However, the metal layer plated using such chemical plating processes is very thin and has unstable electrical properties.